In the fields of signal sampling and other high frequency applications, timing signals of up to 10 GHz or more are often used to control switches or other circuit elements.
One example is sampling circuitry, such as a track and hold circuit of an analog to digital converter (ADC). In such an ADC, the track and hold circuit is controlled by a clock signal to store an input signal at a given time instant. In some embodiments, the timing signal is generated by converting low noise differential signals, for example provided by CML (current mode logic). Indeed, low noise differential transmission is often the preferred solution for transmitting high frequency timing signals across an integrated circuit. The generation of the timing signal based on the low voltage differential signal usually involves amplifying the signal to generate a single-ended signal having a voltage swing corresponding to the transistor technology used in the switches of the receive circuit.
However, a problem is that existing solutions for converting such differential signals into a single-ended full-swing signal tend to add jitter to the timing signal. There is thus a need in the art for an improved conversion circuit.